A structure of a main board of a common electronic apparatus or a computer system is composed of a central processing unit (CPU), a control chip, a system memory and peripheral circuits. The control chip controls operations between the CPU and peripheral apparatuses, e.g., data access of the system memory. DRAM, is classified as two types—a synchronous (SDRAM) and a double data rate synchronous dynamic random access memory (DDR SDRAM).
Refer to FIG. 1a showing a block diagram of a memory controller 10 and a system memory 11. For different computer systems, the memory controller 10 may reside in a control chip or a predetermined chip. When commands of a computer system are performed, memory space inside the system memory 11 is needed for temporarily storing data. For a data access process performed by the system memory 11, a read operation, a write operation or a refresh operation is controlled by the memory controller 10.
Generally, the system memory 11 is provided with a clock signal generated by the memory controller 10 to perform the access operation according to the clock signal. Under normal operations, the memory controller 10 generates a memory clock signal DCLK having a phase and a frequency synchronous with a reference clock signal CLK (not shown) to the system memory 11, which performs synchronous signal adjustment by implementing a delay-locked loop (DLL) (not shown). Upon the write operation, the memory controller 10 generates a data strobe signal DQS. Upon the read operation, the data strobe signal DQS and associated data are transmitted back to the memory controller 10, such that the control chip access the data of the system memory 11 according to the data strobe signal DQS.
The synchronous adjustment performs a delayed input and/or output detection and calibration process on the input memory clock signal DCLK by the DLL, such that a phase of the data strobe signal DQS is synchronous with that of the memory clock signal DCLK. In addition, the DLL continuously compensates the memory clock signal DCLK during the data access process to avoid the skew of the data strobe signal DQS caused by temperature increase or voltage variance of internal components when the computer system is under normal operation status.
Refer to FIG. 1b showing a timing diagram of a data signal DATA and a corresponding data strobe signal DQS. A dual data rate (DDR) system memory samples data at a rising edge and a falling edge of the data strobe signal DQS. In FIG. 1b, signal skew occurs when the phase of the data signal DATA is not aligned with that of the data strobe signal DQS. The rising edge and the falling edge of the data strobe signal DQS are present at transitions of the data signal DATA, thus data access errors occur.
Although the DLL adjusts the memory clock signal DCLK to an original extent in response to ambient variations, signal skew may occur in the data access process due to the ambient variations and uncertain factors of hardware components as components or circuits become more complicated, and thus the DLL on the electronic apparatus or the computer system operates abnormally.
For example, when a digital television (TV) operates, video signals, audio signals and on screen display (OSD) setting information need to be processed, with the signals or information being temporarily stored in a DRAM according to a predetermined priority. A program designer adjusts the phase of the data strobe signal DQS according to characteristics of the hardware components in the factory to facilitate the memory controller accessing the system memory. However, due to different characteristics of hardware components and different operating conditions, the adjusted apparatuses may abnormally operate when processing information for a long tme, and cannot continue to operate normally via original settings by the factory, e.g., image display errors or audio pop sound. The prior art adjusts one by one the apparatuses with the foregoing problems thus resulting in great inconvenience of manufactures and users.